Alif Semiconductor /AE722F80F55D5AS_CM55_HP_View /USB /GUSB2PHYCFG0

HS/FS timeout calibration. The number of PHY clocks, as indicated by the application in this bit field, is multiplied by a bit-time factor; this factor is added to the High-Speed/Full-Speed interpacket timeout duration in the controller to account for additional delays introduced by the PHY. This may be required, since the delay introduced by the PHY in generating the LineState condition may vary among PHYs. The USB standard timeout value for high-speed operation is 736 to 816 (inclusive) bit times. The USB standard timeout value for Full-Speed operation is 16 to 18 (inclusive) bit times. The application must program this field based on the speed of connection. The number of bit times added per PHY clock are: High-Speed operation:

• One 30-MHz PHY clock = 16 bit times
• One 60-MHz PHY clock = 8 bit times Full-Speed operation:
• One 30-MHz PHY clock = 0.4 bit times
• One 60-MHz PHY clock = 0.2 bit times
• One 48-MHz PHY clock = 0.25 bit times

PHY interface. If UTMI+ is selected, the application uses this bit to configure the controller to support a UTMI+ PHY with an 8- or 16-bit interface.

0 (Val_0x0): 8 bits

1 (Val_0x1): 16 bits

ULPI or UTMI+ selection.

0 (Val_0x0): UTMI+ interface

1 (Val_0x1): ULPI interface

Full-Speed serial interface select. Note: USB 1.1 full-speed serial interface is not supported. This bit always reads as 0x0.

Suspend USB2.0 HS/FS/LS PHY. When this bit is set, USB2.0 PHY enters Suspend mode if Suspend conditions are valid. Application needs to set it to 0x1 after the controller initialization completes. Note: In Host mode, on reset, this bit is set to 0x1. Software can override this bit after reset. In Device mode, before issuing any device endpoint command, disable this bit and enable it after the command completes. If the user issues a command without disabling this bit when the device is in L2 state and if MAC2_CLK (UTMI_CLK/ULPI_CLK) is gated off, the command will not get completed.

USB 2.0 High-Speed PHY or USB 1.1 Full-Speed serial transceiver select. Note: USB 1.1 full-serial transceiver is not supported. This bit always reads as 0x0.

Enable UTMI_SLEEP_n and UTMI_L1_SUSPEND_n. The application uses this bit to control UTMI_SLEEP_n and UTMI_L1_SUSPEND_n assertion to the PHY in the L1 state. Note: This bit must be set to 0x1. Note: In Device mode, before issuing any device endpoint command, disable this bit and enable it after the command completes. Without disabling this bit, if a command is issued when the device is in L1 state and if MAC2_CLK (UTMI_CLK) is gated off, the command will not get completed.

0 (Val_0x0): UTMI_SLEEP_n and UTMI_L1_SUSPEND_n assertion from the controller is not transferred to the PHY.

1 (Val_0x1): UTMI_SLEEP_n and UTMI_L1_SUSPEND_n assertion from the controller is transferred to the PHY.

Transceiver Delay. Enables a delay between the assertion of the UTMI Transceiver Select signal (for HS) and the assertion of the TxValid signal during a HS Chirp. When this bit is set to 0x1, a delay (of approximately 2.5 us) is introduced from the time when the Transceiver Select is set to 0x0 (HS) to the time the TxValid is driven to 0 for sending the chirp-K. This bit is valid only in device mode.

USB 2.0 turnaround time. This bit field sets the turnaround time in PHY clocks. Specifies the response time for a MAC request to the Packet FIFO Controller (PFC) to fetch data from the DFIFO (SPRAM). The following are the required values for the minimum SoC bus frequency of 60 MHz. USB turnaround time is a critical certification criteria when using long cables and five hub levels. The required values for this field: Note: This field is valid only in Device mode.

5 (Val_0x5): When the MAC interface is 16-bit UTMI+.

9 (Val_0x9): When the MAC interface is 8-bit UTMI+/ULPI.

LS inter-packet time. This field indicates the value of Tx-to-Tx packet gap for LS devices. The encoding is as follows: Note: This field is applicable only in Host mode. For normal operation (to work with most LS devices), set the default value of this field to 0x2 (3 bit times). The programmable LS device inter-packet gap and turnaround delays are provided to support some legacy LS devices that might require different delays than the default/fixed ones. Include PHY delays when programming the LSIPD/LSTRD values.

0 (Val_0x0): 2 bit times

1 (Val_0x1): 2.5 bit times

2 (Val_0x2): 3 bit times

3 (Val_0x3): 3.5 bit times

4 (Val_0x4): 4 bit times

5 (Val_0x5): 4.5 bit times

6 (Val_0x6): 5 bit times

7 (Val_0x7): 5.5 bit times

LS turnaround time. This bit field indicates the value of the Rx-to-Tx packet gap for LS devices. The encoding is as follows: Note: This field is applicable only in Host mode. For normal operation (to work with most LS devices), set the default value of this bit field to 0x0 (2 bit times). The programmable LS device inter-packet gap and turnaround delays are provided to support some legacy LS devices that might require different delays than the default/fixed ones. Include PHY delays when programming the LSIPD/LSTRD values. For example, if PHY’s TXENDDELAY in LS mode is 30 UTMI CLKs, then subtract this delay (~1 LS bit time) from the device delay requirement.

0 (Val_0x0): 2 bit times

1 (Val_0x1): 2.5 bit times

2 (Val_0x2): 3 bit times

3 (Val_0x3): 3.5 bit times

4 (Val_0x4): 4 bit times

5 (Val_0x5): 4.5 bit times

6 (Val_0x6): 5 bit times

7 (Val_0x7): 5.5 bit times

Overriding the FS/LS disconnect time to 32 us. If this value is 0x0, the FS/LS disconnect time is set to 2.5 us as per the USB specification. If this value is non-zero, the disconnect detection time is set to 32 us.

Reserved.

Reserved.

Reserved. Keep at 0x0.

U2 Free Clock Exists. This bit specifies whether USB 2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active.

0 (Val_0x0): USB 2.0 free clock does not exist

1 (Val_0x1): USB 2.0 free clock exists

UTMI PHY soft reset. Causes the USB2PHY_RESET signal to be asserted to reset a UTMI PHY.